library verilog;
use verilog.vl_types.all;
entity cnt100 is
    port(
        ge_021          : out    vl_logic_vector(3 downto 0);
        sw_clear_021    : in     vl_logic;
        shi_021         : out    vl_logic_vector(3 downto 0);
        CLK_021         : in     vl_logic;
        sw_stop_021     : in     vl_logic
    );
end cnt100;
